1. Field of the Invention
The present invention relates to an emitter coupled logic circuit, and more specifically to such a circuit having a rapid output voltage falling-down property.
2. Description of Related Art
At present, emitter coupled logic circuits have been used in various kinds of electronic circuits. Referring to FIG. 1, there is shown a circuit diagram of a conventional typical emitter coupled logic circuit. The shown circuit includes a first NPN transistor Q10 having a base connected to an input terminal 10 and a collector connected through a resister R to a high voltage line so as to receive a collector supply voltage V.sub.CC. An emitter of the first NPN transistor Q10 is commonly connected to an emitter of another or second NPN transistor Q20, which in turn have a base connected to a reference voltage Vref and a collector connected directly to the high voltage line of the collector supply voltage V.sub.CC. The commonly connected emitters of the first and second NPN transistors Q10 and Q20 are connected through a constant current source I.sub.20 to a low voltage line for an emitter supply voltage V.sub.EE. A connection nobe between the resister R and the collector of the first NPN transistor Q10 is connected to a base of a third NPN transistor Q30, whose collector is in turn connected directly to the high voltage line of the collector supply voltage V.sub.CC. An emitter of the third NPN transistor Q30 is connected to an output terminal 12 and also connected through another constant current source I.sub.30 to the low voltage line of the emitter supply voltage V.sub.EE. In addition, a load capacitance C.sub.L formed due to a wiring capacitance and others exists between the output terminal 12 and the high voltage line of the collector supply voltage V.sub.CC.
In the above mentioned emitter coupled logic circuit, the reference voltage Vref is set at an intermediate voltage between a high level voltage and a low level voltage of an input signal V.sub.IN applied to the input terminal 10. Therefore, if the input signal V.sub.IN is at the high level, the transistor Q10 is turned on, and the transistor Q20 is turned off. Accordingly, a collector current will flow through the transistor Q10, so that a corresponding voltage drop will occur across the resister R. Namely, a potential on the collector of the transistor Q10 will drop. As a result, since the transistor Q30 forms an emitter follower, an output signal voltage V.sub.OUT appearing on the output terminal 12 is brought to a low voltage expressed as follows: EQU V.sub.OUT =V.sub.CC -(R.multidot.I.sub.20 +V.sub.BEQ30)
where V.sub.BEQ30 is a base-emitter voltage of the transistor Q30.
On the other hand, if the input signal V.sub.IN is at the low level, the transistor Q10 is turned off, and the transistor Q20 is turned on. Therefore, the collector current will not flow through the transistor Q10, so that the potential on the collector of the transistor Q10 will be almost V.sub.CC and the transistor Q30 is turned on. As a result, the voltage V.sub.OUT is brought to a high voltage expressed as follows: EQU V.sub.OUT =V.sub.CC -V.sub.BEQ30
Therefore, the shown circuit operates as an inverter having an output logic amplitude of R.multidot.I.sub.20.
In the above mentioned emitter coupled logic circuit, when the potential V.sub.OUT of the output terminal 12 is caused to change from the low level to the high level, an electric charge stored in the capacitance C.sub.L is discharged by an emitter current of the transistor Q30, with the result that the output potential V.sub.OUT is brought to the high level. On the other hand, when the potential V.sub.OUT of the output terminal 12 is caused to change from the high level to the low level, the capacitance C.sub.L is charged by the constant current source I.sub.30 with the result that the output potential V.sub.OUT is brought to the low level. In this connection, it has been an ordinary practice that a current capacity of the constant current source I.sub.30 is much smaller than the emitter current of the transistor Q30. Accordingly, the falling-down time of the output potential V.sub.OUT is considerably larger than the rising-up time of the output potential V.sub.OUT.